How a PCI Express Link Trains

What comes up when a link comes up

A PCI Express link is not wide by default: during device initialization the two ends negotiate how many lanes will carry traffic, and either end can restrict the result. This page stays with what its source states exactly: the four traces in a lane, the negotiation of the width, the pins that hold the handshake, and what changes once the link is trained.

A link is a point-to-point channel between two PCI Express ports, carrying ordinary PCI requests, configuration, I/O or memory reads and writes, and interrupts, INTx, MSI or MSI-X, in both directions. Each device gets its own serial connection to the root complex, the host end of the tree, instead of sharing one set of address, data and control lines the way the older PCI bus did, arbitrated to one master at a time, in a single direction. A PCI Express link is full-duplex between its two endpoints, and concurrent traffic across multiple endpoints carries no inherent limitation.

The state machine that runs this sequence has a name in the specification of the interface beneath it: the PIPE specification, revision 7.1 of September 2025, Intel reference number 643108, calls it the Link Training and Status State Machine, or LTSSM, and its normative text names the states Detect.Quiet, Polling, Configuration, Recovery, L0, L0s, L1, L2, Loopback and Disabled. That document names them rather than defining them one by one, so what follows says what the states are called and what the specification shows them doing, and marks the rest as common industry usage.

Four traces, two pairs, no external clock

A lane is two differential signaling pairs, one to receive and one to transmit, four wires or signal traces in all, and it behaves as a full-duplex byte stream, moving data packets as eight-bit bytes in both directions at once. There is no external clock to distribute, because clocking information is embedded in the serial signal itself. That is the trade that buys the rates: a parallel interface races timing skew, signals arriving at different times on conductors of different lengths and velocities, and once the clock period drops below the widest arrival spread, the transmitted word cannot be recovered, which caps such a bus in the hundreds of megahertz against the multi-gigahertz range of serial signaling. In a multi-lane link, packet data is striped across the lanes, and peak throughput scales with the overall width. The PHY layer that implements the electrical side of this is described on the page on the PIPE interface.

Who decides how wide the link runs?

The lane count is negotiated automatically during device initialization, and either endpoint can restrict it. A single-lane card inserted into a multi-lane slot, x4, x8 and so on, comes out of initialization at the highest lane count both ends support. The standard defines widths of x1, x2, x4, x8 and x16, and up to and including PCIe 5.0 it also defined x12 and x32, which the Wikipedia article on PCI Express, read on September 6, 2026, calls virtually never used. When bad or unreliable lanes are present, the link can dynamically down-configure itself onto fewer of them, which reads as failure tolerance rather than as a fault.

The socket can misrepresent itself too. A x16 slot may wire only four lanes, accepting any card while providing four, and its line in a specification reads x16 (x4 mode), x16 (x4 signal), or the shorthand x16 @ x4. The table below collects the widths and where the page meets them.

The pins that hold the handshake

Training rests on services the edge connector provides. PERST# is the fundamental reset, listed in the pinout as link reactivation. REFCLK+ and REFCLK- form the reference clock differential pair, and CLKREQ# is the clock request signal. Presence has its own mechanism: the PRSNT1# and PRSNT2# pins are slightly shorter than the rest, so they only make contact when a hot-plugged card is fully inserted. WAKE# closes the set, pulled high from standby power to say the card is wake capable. The mechanical side, sizes, brackets, open-ended sockets that accept longer cards, sits on the page that walks through the card and the slot.

What changes once the link is trained?

Once traffic flows, communication is encapsulated in packets, and the transaction layer of each PCI Express port does the packetizing and de-packetizing of data and status-message traffic. The software view is quieter: PCI Express preserves backward compatibility with PCI, so legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the standard, with the newer features left inaccessible.

The power budget moves as well. A x1 card is held to 0.5 A at +12 V, 6 W, and 10 W combined, while a full-sized x1 card, initialized and software-configured as a high-power device, may draw up to 25 W. A full-sized x16 graphics card may draw up to 5.5 A at +12 V, 66 W, and 75 W combined on the same conditions. Far above those numbers, the summary line of the source page gives a top speed of up to 242 GB/s, labeled dual simplex; what encoding leaves of that figure is a separate question, treated on the encoding and usable bandwidth page.

Reading a link that trained narrow

A narrow link, not a dead one, is what usually reaches the bench. The card sits in a x16 socket, the driver loads, and transfers never clear a x4 ceiling. Read the documentation before reaching for instruments: the slot line gives the electrical width away, and either endpoint may have restricted the count during initialization. Then work from the connector backward, reset and reference clock first.

On the next board that trains narrow, find the line that pairs the mechanical size with the electrical one, and ask which endpoint could have restricted the count. If the answer is neither, watch the link come up after a fundamental reset and see whether the width it settles on matches the width on paper. Where the two disagree, the connector is the first suspect, not the negotiation.