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Root ComplexReading the PCI Express link

Section 02

Generations

One rate ladder from 2.5 GT/s to 64 GT/s, the two encodings that sit under it, and the difference between a transfer rate and a usable byte rate.

Five add in cards of different ages laid out in a row on a workbench, oldest on the left, their gold contact fingers catching the light

One ladder, doubled at every rung

Each numbered generation of PCI Express roughly doubles the raw per lane transfer rate of the one before it. The ladder runs 2.5, 5.0, 8.0, 16.0, 32.0, 64.0 and 128.0 gigatransfers per second per lane, and every one of those rates is named in the rate tables of the PIPE specification revision 7.1 read for this site. What changes between rungs is not only the number: keeping a doubled rate intact across a real board required changes to encoding, to equalization and, at the top of the ladder, to the signaling itself.

Why is 8 GT/s worth more than 1.6 times 5 GT/s?

Because the encoding changed. The first two generations wrap eight bits of payload in ten bits on the wire, which spends a fifth of the line rate on the encoding. From the third generation the wrapper becomes 128 bits of payload in 130 bits on the wire, and the same table of contents that names the rates ties that scheme to 8, 16 and 32 GT/s. The line overhead falls from about a fifth to a little over one percent, so the usable byte rate very nearly doubles even though the transfer rate rose by a factor of 1.6. That arithmetic, and the difference between a transfer rate and a byte rate, is worked through in encoding and usable bandwidth.

What changed at the top of the ladder

The pattern of pushing two level signaling faster does not continue indefinitely. The sixth generation moves to four level pulse amplitude modulation with forward error correction, and introduces a fixed size flow control unit in place of the older variable length framing. The seventh doubles again from there. The consequence for a reader is practical: a board budget written for a two level link does not transfer to a four level one, and a figure quoted without its generation is not a figure at all.

Which number belongs on a page?

This site publishes the per lane transfer rate as the headline number because it is the one that appears in the specification and in the tables of a physical interface document. Usable byte rates are derived, and derived values are printed next to their derivation rather than presented as published figures. The full set, generation by generation, with the source of each row, is the link speed table, and the story of what changed at each step is the rate ladder.

What is still open

Publication dates are the weak part of this section. For several generations the desk could confirm only the year, and it says so on the page rather than printing a precise date it cannot support. The reading that would close the gap is named in sources and method.

The other doors of the publication: Link Basics, Form Factors, Compliance, Topology, Ecosystem and Bench Notes. Every one of them points back to the link speed table.

02

In this section

10 pages, newest first.

  1. Several expansion cards from different years standing upright in a row in a foam block, their gold contact fingers aligned and lit from above

    The Rate Ladder, Generation by Generation

    Each generation of the base specification doubles the per lane transfer rate. The interesting part is what had to change underneath to make that doubling survive a real board.

    September 6, 2026

  2. A logic analyzer screen filled with parallel digital traces, the cursor lines measuring the width of one symbol against a time scale

    Encoding, Overhead and Usable Bandwidth

    A transfer rate counts symbols on the wire. A byte rate counts what reaches the other side. The gap between the two is the encoding, and it changed once.

    September 6, 2026

  3. Two generations of expansion cards side by side on a bench, the newer one shorter, both showing the same edge connector pattern

    What a revision keeps fixed

    A specification revision is a calendar with fixed and movable feasts, and the reader who knows which is which reads it in minutes.

    September 6, 2026

  4. An old white PCI slot beside a newer black PCI Express slot on the same motherboard, photographed at an angle under bench light

    The PCI to Express break: kept and cut

    The mechanism was replaced and the contract kept, which is why old system software still enumerates the newest hardware.

    September 6, 2026

  5. A close-up of a PCIe x16 slot on a server motherboard under cool white bench light, with a riser cable entering the connector and the retention clip in sharp focus.

    Rate negotiation between PCIe generations

    Two PCI Express ports agree on a rate by advertising the speeds each one supports during link training, then settling on the highest rate that appears in both lists.

    September 6, 2026

  6. A laboratory bench at night: a PCI Express Gen6 protocol analyzer with its screen showing three stacked eye openings, a short coaxial cable looping to a test board, and a desk lamp casting a hard pool of light on the connector.

    PAM4 and the Gen6 signal: Four levels, less margin

    PAM4 replaces the two-level NRZ eye of earlier PCI Express generations with a four-level signal, so each unit interval carries two bits instead of one.

    September 6, 2026

  7. A printed specification open on a desk beside a laptop, the revision number on the cover page visible under a warm desk lamp, shot from a low angle across the table.

    Figures and editions: Quoting a rate table

    A figure belongs to the revision that published it, not to the device it describes.

    September 6, 2026

  8. Five expansion cards of different ages fanned out on a dark bench, their gold contact fingers overlapping like the steps of a staircase

    The Link Speed Table

    One table, one row per generation, and a column that says where the figure came from. Everything else on this site refers back to it.

    September 6, 2026

  9. A chalkboard above a lab bench with a bandwidth calculation written out line by line, each deduction crossed and a final figure circled

    What the usable rate is made of

    The rate on the ladder is the bottle strength; the usable bandwidth is the drink, and the deductions are the mixer.

    September 5, 2026

  10. A notebook page with a column of small percentage figures added down the margin beside a protocol analyzer trace on a screen

    The arithmetic of overhead

    Nothing on the bill looks large, and the bill is the difference between the rate on the label and the rate in the trace.

    September 5, 2026