The Rate Ladder, Generation by Generation

Seven rates, one rate table

PCI Express organizes its history into numbered generations, each one roughly doubling the raw transfer rate of a single lane and changing the line encoding when the overhead of the old one stops being acceptable. The material read for this page on September 6, 2026 gives seven raw rates per lane: 2.5, 5.0, 8, 16, 32, 64 and 128 GT/s. The same seven values appear in the rate tables of the PIPE specification, revision 7.1, dated September 2025, Intel reference number 643108, the document that defines the PHY interface a lane is built on. Two lists, one ladder. The highest named rate belongs to generation 7.0.

Dates in the second column go to the day only where the material read supports it; the first three rows are dated to a year or a range.

The 8b/10b years

Generation 1.0 and its 1.0a revision were released in 2003, and 1.1 followed in 2005. All run at 2.5 GT/s per lane with 8b/10b encoding, which carries a fixed 20 percent of the line away as overhead and leaves about 250 MB/s of useful throughput per lane, per direction. Generation 2.0 in 2007 and 2.1 in 2009 doubled the raw rate to 5.0 GT/s and kept the encoding, so the useful figure doubled with it, to about 500 MB/s per lane, per direction. This is the stretch of the ladder where a fifth of the line rate goes before a packet moves. The exact publication date for 2.1 is not confirmed beyond the year 2009 in the material read, so the table stops at the year.

Why did 8 GT/s almost double the useful rate?

Generation 3.0 was finalized and officially published by PCI-SIG on 18 November 2010, at 8.0 GT/s per lane. The raw rate rose by a factor of 1.6; the useful figure almost doubled, to about 0.985 GB/s per lane, per direction. The difference is the encoding: 3.0 replaced 8b/10b with 128b/130b, which cuts line overhead from about 20 percent to roughly 1.54 percent. 3.0 also introduced transmitter and receiver equalization, PLL improvements, clock data recovery and channel enhancements. Generation 3.1 stayed at 8.0 GT/s and arrived around 2013-2014; the exact date is unconfirmed rather than guessed. The ladder is also tabulated in the public PCI Express article the desk read as its secondary source, and its rate column matches the one above.

One encoding holds from 8 to 32 GT/s

Generation 4.0 was released on 8 June 2017, at 16.0 GT/s per lane and about 1.969 GB/s of useful throughput per lane, per direction. Generation 5.0 followed on 29 May 2019, at 32.0 GT/s per lane and about 3.938 GB/s. Neither row changes the encoding. The PIPE layer table ties 128b/130b to "PCIe 8, 16, and 32 GT/s", so three generations of raw rates run under one overhead figure, and the useful column doubles cleanly from 0.985 to 1.969 to 3.938 GB/s. A GT/s figure alone overstates an 8b/10b part by about a fifth and a 128b/130b part by about 1.54 percent. That subtraction is written out on the page about encoding and usable bandwidth.

What changes at 64 GT/s?

Generation 6.0, released on 11 January 2022, stops pushing two-level signaling faster and moves to PAM4, four-level pulse-amplitude modulation, at 64.0 GT/s per lane. PAM4 is noisier than the NRZ signaling used before it, and the specification pairs it with a low-latency forward error correction scheme to stay reliable. The framing changes too: FLIT mode becomes mandatory, a fixed 256-byte block carrying 242 bytes of usable payload, TLPs and DLLPs together, replacing the variable-length framing used at lower generations. The net useful figure is about 7.563 GB/s per lane, per direction. The raw rate doubled; the machinery underneath it changed shape.

The top rung, and what this page cannot confirm

Generation 7.0 was released on 11 June 2025, doubling the raw rate again to 128.0 GT/s per lane and continuing PAM4 plus forward error correction, for about 15.125 GB/s of useful throughput per lane, per direction. One cross-check: the Linux kernel's PCI error-recovery documentation cites "PCIe r7.0" as the current base specification revision, which lines up with that release date. Two limits stand. The day and month of release for generations 1.0, 1.1, 2.0, 2.1 and 3.1 are not in the material read for this page. And nothing in that material names a per-lane rate above 128 GT/s, so this ladder stops at seven rungs rather than eight.

A GT/s figure is a line rate. What a link carries is what survives the encoding, and the encoding changed twice on this ladder.

Take the rate a datasheet gave you, find its row in the link speed table, then check the PIPE rate tables for the same rate and the encoding you assumed. If the two disagree, one of them is not the figure you were quoting.