https://pciexpressdevnet.org/ An independent reference on PCI Express: lane rates, link training, form factors, topology, compliance and the vendor categories that fill a solutions catalog. en-us https://pciexpressdevnet.org/link-basics/how-a-link-trains/https://pciexpressdevnet.org/link-basics/how-a-link-trains/Sun, 06 Sep 2026 00:00:00 +0000Detect, Polling, Configuration, L0: what the training state machine does between power on and the first packet, and why a link can settle below its width. https://pciexpressdevnet.org/link-basics/what-the-pipe-interface-is/https://pciexpressdevnet.org/link-basics/what-the-pipe-interface-is/Sun, 06 Sep 2026 00:00:00 +0000PIPE is the boundary between a PCI Express controller and its physical layer. What it standardizes, which architectures it covers, and who publishes it. https://pciexpressdevnet.org/link-basics/reading-a-sequence-in-counts/https://pciexpressdevnet.org/link-basics/reading-a-sequence-in-counts/Sun, 06 Sep 2026 00:00:00 +0000Detect, Polling, Configuration, L0: the LTSSM read as a counted sequence, one state per count, for the reader meeting it for the first time. https://pciexpressdevnet.org/link-basics/the-states-that-hold-a-link-back/https://pciexpressdevnet.org/link-basics/the-states-that-hold-a-link-back/Sun, 06 Sep 2026 00:00:00 +0000L0s, L1 and L2: the negotiated pauses inside the training machine, what they cost in exit latency, and how ASPM decides which are allowed. https://pciexpressdevnet.org/link-basics/link-equalization-explained/https://pciexpressdevnet.org/link-basics/link-equalization-explained/Sun, 06 Sep 2026 00:00:00 +0000How a link at 8 GT/s and above measures its channel and tunes transmitter and receiver settings before carrying traffic, and what training negotiates. https://pciexpressdevnet.org/link-basics/ordered-sets-dllp-and-tlp/https://pciexpressdevnet.org/link-basics/ordered-sets-dllp-and-tlp/Sun, 06 Sep 2026 00:00:00 +0000Ordered sets, DLLPs and TLPs are the three vocabularies of a PCI Express link. What each layer sends, what it guarantees, and how to tell them apart in a https://pciexpressdevnet.org/link-basics/reading-what-a-device-says-about-itself/https://pciexpressdevnet.org/link-basics/reading-what-a-device-says-about-itself/Sun, 06 Sep 2026 00:00:00 +0000How a PCI Express function reports its capabilities, what those bits may claim, and how to audit one function against its datasheet. https://pciexpressdevnet.org/generations/the-rate-ladder/https://pciexpressdevnet.org/generations/the-rate-ladder/Sun, 06 Sep 2026 00:00:00 +0000From 2.5 GT/s to 64 GT/s per lane: what each generation of PCI Express changed, and why the headline number roughly doubles every time. https://pciexpressdevnet.org/generations/encoding-and-usable-bandwidth/https://pciexpressdevnet.org/generations/encoding-and-usable-bandwidth/Sun, 06 Sep 2026 00:00:00 +0000Why 8 GT/s is not twice 5 GT/s in practice: 8b/10b, 128b/130b and the difference between a transfer rate and the bytes a device actually moves. https://pciexpressdevnet.org/generations/what-a-revision-keeps-fixed/https://pciexpressdevnet.org/generations/what-a-revision-keeps-fixed/Sun, 06 Sep 2026 00:00:00 +0000Each generation changes the per-lane rate and keeps the architecture: lanes, links, packets, configuration space and the connector contract. https://pciexpressdevnet.org/generations/the-pci-to-express-break/https://pciexpressdevnet.org/generations/the-pci-to-express-break/Sun, 06 Sep 2026 00:00:00 +0000Parallel shared wires gave way to serial point-to-point lanes while configuration space and the software model survived almost untouched. https://pciexpressdevnet.org/generations/rate-negotiation-between-generations/https://pciexpressdevnet.org/generations/rate-negotiation-between-generations/Sun, 06 Sep 2026 00:00:00 +0000How two PCIe ports advertise supported rates during training, settle on the highest shared rate, and what a fallback below the board design costs.