https://pciexpressdevnet.org/ An independent reference on PCI Express: lane rates, link training, form factors, topology, compliance and the vendor categories that fill a solutions catalog. en-us https://pciexpressdevnet.org/link-basics/how-a-link-trains/https://pciexpressdevnet.org/link-basics/how-a-link-trains/Sun, 06 Sep 2026 00:00:00 +0000Detect, Polling, Configuration, L0: what the training state machine does between power on and the first packet, and why a link can settle below its width. https://pciexpressdevnet.org/link-basics/what-the-pipe-interface-is/https://pciexpressdevnet.org/link-basics/what-the-pipe-interface-is/Sun, 06 Sep 2026 00:00:00 +0000PIPE is the boundary between a PCI Express controller and its physical layer. What it standardizes, which architectures it covers, and who publishes it. https://pciexpressdevnet.org/generations/the-rate-ladder/https://pciexpressdevnet.org/generations/the-rate-ladder/Sun, 06 Sep 2026 00:00:00 +0000From 2.5 GT/s to 64 GT/s per lane: what each generation of PCI Express changed, and why the headline number roughly doubles every time. https://pciexpressdevnet.org/generations/encoding-and-usable-bandwidth/https://pciexpressdevnet.org/generations/encoding-and-usable-bandwidth/Sun, 06 Sep 2026 00:00:00 +0000Why 8 GT/s is not twice 5 GT/s in practice: 8b/10b, 128b/130b and the difference between a transfer rate and the bytes a device actually moves. https://pciexpressdevnet.org/form-factors/the-card-slot-explained/https://pciexpressdevnet.org/form-factors/the-card-slot-explained/Sun, 06 Sep 2026 00:00:00 +0000x1, x4, x8 and x16 connectors, the break in the contact fingers, the power a slot delivers and what happens when a long card sits in a short slot. https://pciexpressdevnet.org/form-factors/m2-keys-and-module-sizes/https://pciexpressdevnet.org/form-factors/m2-keys-and-module-sizes/Sun, 06 Sep 2026 00:00:00 +0000What the letter key on an M.2 socket actually restricts, how the length codes are read, and why a module that fits mechanically can still refuse to work. https://pciexpressdevnet.org/compliance/reading-a-receiver-eye/https://pciexpressdevnet.org/compliance/reading-a-receiver-eye/Sun, 06 Sep 2026 00:00:00 +0000What the opening of an eye actually measures, how a mask turns a picture into a pass or a fail, and what jitter and voltage margin mean on that display. https://pciexpressdevnet.org/compliance/how-a-compliance-program-works/https://pciexpressdevnet.org/compliance/how-a-compliance-program-works/Sun, 06 Sep 2026 00:00:00 +0000Compliance workshops, the integrators list and the logo: what each one certifies, what it does not, and how a reader should weigh the claim on a datasheet. https://pciexpressdevnet.org/topology/root-ports-switches-endpoints/https://pciexpressdevnet.org/topology/root-ports-switches-endpoints/Sun, 06 Sep 2026 00:00:00 +0000The shape of a PCI Express hierarchy: what a root complex owns, what a switch adds, what a bridge is for, and where an endpoint sits in the tree. https://pciexpressdevnet.org/topology/enumeration-and-configuration-space/https://pciexpressdevnet.org/topology/enumeration-and-configuration-space/Sun, 06 Sep 2026 00:00:00 +0000How firmware walks the hierarchy at boot, what bus, device and function numbers mean, and what a base address register is actually reserving. https://pciexpressdevnet.org/ecosystem/bridges-and-switches/https://pciexpressdevnet.org/ecosystem/bridges-and-switches/Sun, 06 Sep 2026 00:00:00 +0000A bridge translates between two buses, a switch fans one link into several. What each part does to traffic, and what a system designer is buying with either. https://pciexpressdevnet.org/ecosystem/ip-cores-and-verification-models/https://pciexpressdevnet.org/ecosystem/ip-cores-and-verification-models/Sun, 06 Sep 2026 00:00:00 +0000Controller cores, PHY cores and bus functional models: three product categories that only make sense once you know which part of a design they replace.