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Root ComplexReading the PCI Express link
Close view of a server backplane with several edge connectors of different lengths lit from the side, copper traces fanning out across the green board
Slots of four different lengths on one board: the width of a connector is the first thing a PCI Express link negotiates.

A reading desk for the serial link

Root Complex

What a lane carries, how a link comes up, which connector holds it, and what a compliance figure actually measures. Written for the person reading a datasheet, not for the person selling the part.

  1. 2.5 GT/s per lane, lowest rate Named in the PIPE 7.1 rate tables
  2. 32 GT/s per lane, 128b/130b The same encoding at 8, 16 and 32 GT/s
  3. 128 GT/s per lane, highest named The top row of the same tables
  4. 7.1 PIPE revision, September 2025 Intel reference number 643108

All four figures are read from one document: the PHY Interface for the PCI Express, SATA, USB 3.2, DisplayPort and USB4 Architectures Specification, revision 7.1, Intel reference 643108, September 2025, read on September 6, 2026. Generation labels and usable byte rates are a separate question, and every row that carries one names its own source. The same figures are published in the link speed table.

01 to 07

The seven sections

From the rulebooks to the ground they are run on.

  1. A single differential pair traced across a green circuit board between two packaged chips, the two lines running side by side at a constant spacing

    PCI Express Link Basics: Lanes, Links and Training

    Lanes, widths, link training and the PHY interface underneath all of it.

    Section 01

  2. Five add in cards of different ages laid out in a row on a workbench, oldest on the left, their gold contact fingers catching the light

    PCI Express Generations and Their Data Rates

    The rate ladder, the encoding under it, and what a generation actually buys you.

    Section 02

  3. A short M.2 module held above the notched socket it belongs to, with a full length expansion card lying flat behind them for scale

    PCI Express Form Factors: Slots, M.2 and Cabled Links

    Slots, keys, module lengths and cables: the same link in different bodies.

    Section 03

  4. A differential probe held on two adjacent test pads of a circuit board by a jointed arm, its coaxial lead sweeping out of the frame to the left

    PCI Express Compliance Testing and Eye Diagrams

    Workshops, integrator lists, eye masks and what a compliance figure proves.

    Section 04

  5. A motherboard photographed from directly above, its expansion slots and chipset package visible as the branches of a fan out from one corner

    PCI Express Topology: Root Complex, Switches and Endpoints

    Root ports, switches, endpoints, enumeration and configuration space.

    Section 05

  6. Dozens of board connectors and controller packages laid out in neat rows on a dark antistatic mat, sorted by size from smallest to largest

    The PCI Express Ecosystem, Category by Category

    The product categories behind a solutions catalog, and what each one covers.

    Section 06

  7. A spiral notebook open beside a probe tip and a coil of coaxial cable on a grey bench mat, handwritten measurements filling the left page

    Bench Notes: Revisions and Reading Notes

    Dated notes: what was read, what was corrected, what changed here.

    Section 07

Reference

The two standing resources

Cited by every section, revised on a dated review.

  1. Five expansion cards of different ages fanned out on a dark bench, their gold contact fingers overlapping like the steps of a staircase

    The Link Speed Table

    Per lane transfer rate, encoding and usable byte rate for every generation, each row carrying its source and its date of reading.

    Reference

  2. A stack of technical binders seen edge on, paper tabs of several colors marking pages deep inside the middle volume

    Glossary of the Link

    The vocabulary a PCI Express datasheet assumes you already have, defined in one or two sentences each.

    Reference

Latest

The register

The nine most recent pages of the publication. The full list lives in each section.

  1. A test board on a bench with a riser card seated in its slot and two probe tips resting on the copper traces beside the connector

    How a PCI Express Link Trains

    Link Basics

    Between power on and the first transaction, the two ends of a PCI Express link run a fixed sequence of states. Knowing that sequence is what turns a stuck link into a readable symptom.

  2. A block diagram printed on paper showing two rectangles joined by a labelled bus, annotated in pencil with signal counts in the margin

    What the PIPE Interface Is, and What It Is Not

    Link Basics

    PIPE is the reason a controller core and a PHY from two different suppliers can be wired together at all. It is an interface specification, not a protocol layer.

  3. Several expansion cards from different years standing upright in a row in a foam block, their gold contact fingers aligned and lit from above

    The Rate Ladder, Generation by Generation

    Generations

    Each generation of the base specification doubles the per lane transfer rate. The interesting part is what had to change underneath to make that doubling survive a real board.

  4. A logic analyzer screen filled with parallel digital traces, the cursor lines measuring the width of one symbol against a time scale

    Encoding, Overhead and Usable Bandwidth

    Generations

    A transfer rate counts symbols on the wire. A byte rate counts what reaches the other side. The gap between the two is the encoding, and it changed once.

  5. Four expansion slots of increasing length on one motherboard, photographed at a low angle so the retention tab of each is visible

    The Card Slot, Read End to End

    Form Factors

    The card electromechanical connector is the part of PCI Express most people can actually see. Almost everything about it is a clue to how the link will come up.

  6. Two small storage modules of different lengths lying beside an open socket with its retaining screw and standoff visible on the board

    M.2 Keys, Module Sizes and What Fits

    Form Factors

    An M.2 socket is a mechanical filter on an electrical question. The key tells you which signal sets the socket may carry, and it is only half of the answer.

  7. A fine two needle differential probe tip resting on two adjacent test pads of a green circuit board, the rest of the board falling out of focus behind it

    Reading a Receiver Eye Diagram

    Compliance

    An eye diagram is thousands of bit periods drawn on top of each other. The shape in the middle is the margin a receiver has left, and the mask is the shape it must clear.

  8. A bench in a test room with a card under test wired to instruments, a printed checklist clipped to the frame above the setup

    How a Compliance Program Works

    Compliance

    A product that passed a compliance workshop passed a defined set of tests on a defined day. That is a useful fact, and it is a narrower one than most marketing copy suggests.

  9. A server motherboard seen from above with its expansion slots, chipset heatsink and processor sockets laid out across the whole board

    Root Ports, Switches and Endpoints

    Topology

    PCI Express is a tree, not a bus. Every device hangs from exactly one path back to the root complex, and most confusing symptoms come from misreading that path.

Start here

Four pages to begin with

The rules, the levels, the screening and the hunting day.

  1. A test board on a bench with a riser card seated in its slot and two probe tips resting on the copper traces beside the connector

    How a PCI Express Link Trains

    Between power on and the first transaction, the two ends of a PCI Express link run a fixed sequence of states. Knowing that sequence is what turns a stuck link into a readable symptom.

    September 6, 2026

  2. Several expansion cards from different years standing upright in a row in a foam block, their gold contact fingers aligned and lit from above

    The Rate Ladder, Generation by Generation

    Each generation of the base specification doubles the per lane transfer rate. The interesting part is what had to change underneath to make that doubling survive a real board.

    September 6, 2026

  3. An open parts cabinet with shallow drawers pulled out at different depths, each drawer holding one family of board connectors

    The Solutions Catalog, Category by Category

    This address used to hold a roster of catalog participants. The roster itself is gone and is not reconstructed here. Its structure survives in the archive, and the structure is the useful part.

    September 5, 2026

  4. A closed archive box of loose printed documents seen from the side on a workbench, only the paper edges visible, a magnifying glass resting on the lid

    Document 300312-001, and Where That Reading Goes Now

    If you arrived from a chipset datasheet looking for document 300312-001, this page tells you what that reference was for and which current documents answer the same question.

    September 5, 2026

This publication is not the PCI Special Interest Group, not a working group and not a chip vendor: it reads public specifications and vendor documentation and writes down what they say, which is set out on the about page. Every figure carries the document it came from and the day it was read, a procedure described in sources and method.