Link Basics

What a lane is, and what a link is

A lane is a pair of differential wires in each direction: two conductors carrying the signal out, two carrying it back. A link is the set of lanes that two ports agree to use together. That distinction is the whole reason a figure quoted in gigatransfers per second is not, by itself, a bandwidth: it describes one lane, in one direction, and the link may be one lane wide or sixteen.

The standard defines link widths of x1, x2, x4, x8 and x16, and up to PCI Express 5.0 it also defined x12 and x32, which were effectively never built. In practice a link between two devices is somewhere between one and sixteen lanes, and the number is decided by the two ends rather than by the connector alone.

Why a link can come up narrower than the slot

The lane count actually used is negotiated when the devices initialize, and either side may restrict it. A card can have fewer lanes wired than the slot accepts. A platform can route fewer lanes to a slot than the slot is long. Both are ordinary, both are silent, and both produce the same symptom: a working device running at a width the buyer did not expect. Reading the negotiated width is therefore the first measurement worth taking, and it is described in enumeration and configuration space.

Where the state machine sits

Bringing a link up is the job of a state machine that the PIPE specification names in full: the Link Training and Status State Machine, abbreviated LTSSM. That document names the states Detect.Quiet, Polling, Configuration, Recovery, L0, L0s, L1, L2, Loopback and Disabled. It describes them from the point of view of the interface it specifies rather than defining each one, so this section says what the specification says and marks the rest as industry usage. The sequence, and what each stage is commonly understood to do, is in how a link trains.

The interface underneath

Below the controller sits the physical layer, and the boundary between them has its own specification. PIPE, currently at revision 7.1 dated September 2025 under Intel reference number 643108, defines that boundary for PCI Express, SATA, USB 3.2, DisplayPort and USB4. It is why a controller core and a PHY from two different suppliers can be wired together at all, and it is covered in the PIPE interface.

Where to go next

Readers who arrived here from a datasheet figure want the numbers first: those are in the link speed table, one row per generation, each row carrying the document it came from. Readers who hit an unfamiliar word will find it defined once in the glossary of the link. Both are revised rather than replaced, and every revision is dated.

The other doors of the publication: Generations, Form Factors, Compliance, Topology, Ecosystem and Bench Notes. Every one of them points back to the link speed table.