Link Basics
Reading a training sequence in counts
The link training state machine is a fixed sequence, and the beginner who learns to count it can find the count a failing link never leaves.
What a counted sequence is
The Link Training and Status State Machine, LTSSM, is a fixed sequence of states the two ends of a PCI Express link walk through between power on and the first packet. This page reads it the way a beginner reads a counted exercise: each state is one count, the order is fixed, and the skill is knowing which count you are on.
The specification does not describe training as a prose narrative. It names states, Detect.Quiet, Polling, Configuration, Recovery, L0, L0s, L1, L2, Loopback and Disabled, and it defines the transitions between them. A first pass through that material is easier if it is treated as a sequence to be counted rather than a mechanism to be admired. Count one is Detect, the state a link drops into at reset, where each end asks whether anything is attached at all. Count two is Polling, where the ends exchange ordered sets and agree on a common rate. Count three is Configuration, where the link settles its width, its lane numbering and its lane reversal. Count four is L0, the working state, the only one in which packets flow.
The convention of learning a sequence by counting its steps is older than this bus. A dance teacher writes a choreography the same way, and a beginner guide like the counted dance sheet shows why: the learner who knows which count the weight lands on can find the place again after a stumble. The LTSSM rewards the same reading. A link that will not train is not a mystery, it is a count the machine never leaves.
The counts, in order
Detect is where the link begins. The transmitter looks for a receiver termination on the other side of the channel; if nothing answers, the machine stays quiet. Polling is the conversation that follows: the two ends swap training sequences that carry their supported rates, and the slower common rate is the one they will first run. Configuration does the arithmetic of width: lanes are numbered, a card in a wider socket settles at the narrower of the two capabilities, and lane reversal or polarity inversion is absorbed here rather than treated as a fault.
L0 is the operational state, the count on which packets actually move. Around it sit the pauses. L0s is a short doze, a brief idle that returns quickly. L1 is a deeper sleep, negotiated rather than entered alone, and L2 is the state before power goes away entirely. Recovery is the way back from those pauses, the count the machine re-runs to re-establish bit and symbol lock without re-doing the whole sequence. Loopback is a test state, entered on instruction, that returns what it receives. Disabled is the state a link is put into on purpose, which the page on who can stop a link treats separately.
How do you tell which count a link is on?
From software, mostly indirectly. The negotiated speed and width are reported in the link status register once the machine reaches L0, and tools such as lspci read them back: LnkSta carries the current speed and the negotiated width, LnkCap carries the maximum the port claims. What software does not see is the intermediate counts. A link sitting in Detect looks like a device that does not exist. A link stuck in Configuration reads as a device that trains and retrains without settling. The distinction matters because the fix differs: Detect problems point at the channel and the connector, Configuration problems at the negotiation itself.
On the bench, the states are visible as activity patterns on the pairs. A link in Polling shows bursts of ordered sets at the lowest common rate; a link in L0 shows scrambled traffic. The electrical side of that boundary is described on the page about the PIPE interface, and the rates the ends can offer are listed in the link speed table.
| State | Count in the sequence | What the source assigns to it |
|---|---|---|
| Detect.Quiet | Entry at reset | Is anything attached to the pairs |
| Polling | Second | Rate agreement through ordered sets |
| Configuration | Third | Width, lane numbering, reversal and polarity |
| L0 | Fourth, the working state | Packets flow in both directions |
| L0s, L1, L2 | Pauses | Idle states of increasing depth |
| Recovery | The way back | Re-lock without a full retrain |
| Loopback, Disabled | Off the line | Test return path, deliberate stop |
Why does the sequence exist at all?
Because nothing about a PCI Express link is pre-agreed. The two ends may be built by different vendors, at different revisions of the standard, in sockets of different widths, and they meet for the first time at power on. The counted sequence is what replaces a configuration file: each count resolves one variable, and the machine does not advance until that variable is settled. Rate first, width second, operation last. The older bus this one replaced solved the same problem by fixing every variable in advance, which is why it needed jumpers and keyed slots, and why it could not change its mind. The comparison is drawn on the page about the PCI to Express break.
The sequence also explains the failure signature that puzzles newcomers: a device that enumerates, then vanishes. The machine reached L0, a pause or an error pushed it back to Recovery, and Recovery did not hold. Reading the symptom as a position in the sequence turns it from intermittent magic into a count that fails.
Checks for reading the sequence
- Read LnkSta before touching the channel: the negotiated speed and width say which count the machine settled on.
- A device absent from enumeration is a link in Detect, not a software problem; look at presence and reset first.
- A link that retrains repeatedly is falling out of a pause state or failing Recovery, which points at signal margin rather than configuration.
- Remember the order: rate is agreed before width, so a rate failure hides every later count.
Common mistakes
- Reading L0 as the whole story. The pauses and Recovery are part of the same machine, and most intermittent links live there.
- Assuming the widest socket trained wide. Configuration settles at the narrower end, and the status register is the only honest answer.
- Treating a missing device as a dead card before checking whether the pairs ever left Detect.
- Quoting the state names without the document. The names come from the PIPE specification; usage of them elsewhere is convention, not text.
On the next link that refuses to come up, count it rather than fighting it. Ask whether the pairs saw a receiver, whether a rate was agreed, whether a width was settled, and whether the working state ever held. The answer to one of those questions is the count the machine cannot pass.
The page behind these facts
The state names and their order come from the PIPE specification, revision 7.1 of September 2025, Intel reference 643108, read on September 6, 2026, which names the LTSSM states without walking them one by one. The register fields and the shared-bus comparison are summarized in the Wikipedia article on PCI Express, read the same day. The document that sent many readers to this desk is document 300312-001.