Glossary of the Link

What an entry has to prove before it lands on this page

A glossary is where a reader goes to stop guessing, so this one runs on a narrow rule: a term is defined here only when a document read for this page supports it, and the document is named before the figure. For the physical layer that document is the PHY Interface for the PCI Express, SATA, USB 3.2, DisplayPort and USB4 Architectures Specification, revision 7.1, September 2025, Intel reference number 643108. Its scope covers PCIe conforming to the PCIe Base Specification, revision 7.0, alongside SATA 3.0, USB 3.2, DisplayPort 2.0 and USB4 v2.0.

What that document does not settle comes from a secondary summary of the standard, read on September 6, 2026. What neither source reached is written as an open item in its own sentence: common industry usage rather than something the desk could trace to a document it read.

Every definition below rests on a named document, and every gap is named as a gap.

Why does a gigatransfer not buy a gigabyte?

A lane is two differential signaling pairs, one to transmit and one to receive, four wires or traces per lane, carrying a full-duplex byte stream in both directions at once. Its raw rate is counted in GT/s, and a transfer is a symbol, not a byte. Encoding decides how many symbols become data: 8b/10b spends ten line bits for every eight data bits and costs a fixed 20 percent, while 128b/130b spends 130 for every 128 and costs about 1.54 percent.

PCIe 3.0 shows the difference. It raised the raw rate from 5.0 to 8.0 GT/s, a factor of 1.6, and usable throughput came close to doubling anyway, from about 500 MB/s to about 0.985 GB/s per lane, per direction, because the encoding changed in the same step. The PIPE rate tables name the PCIe signaling rates 2.5, 5.0, 8, 16, 32, 64 and 128 GT/s, and the layer table lists 8b/10b and 128b/130b among the encodings a PHY may implement. The usable figures and release dates below come from the PCI Express article on Wikipedia, read on September 6, 2026.

From PCIe 6.0 the framing changes with the signaling: FLIT mode becomes mandatory, a fixed 256-byte block carrying 242 bytes of usable payload with TLPs and DLLPs packed together. Day and month are confirmed for 3.0 through 7.0; the material read gives only years for 1.0, 1.1, 2.0 and 2.1, and nothing beyond 2009 for 2.1. The same figures are worked from the other end on the encoding and usable bandwidth page, and kept row by row in the link speed table.

The words that name what moves between two ports

A link is a point-to-point communication channel between two PCI Express ports, over which both sides exchange ordinary requests (configuration, I/O, or memory read and write) and interrupts. Each runs up to a root complex, the host-side component that ties processor and memory to the PCIe hierarchy, or to a switch that fans one upstream port out across several downstream ports. The page on root ports, switches and endpoints follows that tree.

Width is next. The standard defines x1, x2, x4, x8 and x16, and up to and including PCIe 5.0 it also defined x12 and x32, two widths virtually never implemented in products. The width a link uses is negotiated during device initialization, and either side can restrict it, which is what lets a narrower card work in a wider slot.

The traffic has a fixed vocabulary. The transaction layer packages it as TLPs: a memory read, a memory write, an I/O request or a configuration request, with a Memory Write header of 3 or 4 32-bit words depending on 32-bit or 64-bit addressing, and a payload up to Max_Payload_Size, typically 128, 256 or 512 bytes. The data link layer adds DLLPs, short packets carrying acknowledgements and flow-control credits, and appends a 2-byte header and a 4-byte LCRC to every TLP so integrity is checked on each hop. Flow control runs on six credit types, posted, non-posted and completion, one credit worth 4 DW or 16 bytes. Those categories set the ordering: a posted write is fire-and-forget, a non-posted request waits for a completion, and that completion echoes the requester's Tag.

What the PIPE document names about bringing a link up

The layer table of the PIPE specification names the state machine that brings a link up: the Link Training and Status State Machine, LTSSM. Its normative text names the states Detect.Quiet, Polling, Configuration, Recovery, L0, L0s, L1, L2, Loopback and Disabled. Those ten names are facts read from a document. The behavior of each state is another matter: this page settles one passage and leaves the rest to the base specification.

The roles most often repeated in industry material assign Detect the search for a partner's electrical presence, Polling the arrival at bit lock, Configuration the negotiation of width, L0 the carrying of traffic, and Recovery the retraining of a degraded link. Those assignments fit the ten names, but this is common industry usage rather than something the desk could trace to a document it read. Use the names freely, and attach a behavior only when you can point at the clause that specifies it, as the page on how a link trains does.

Which words does this desk decline to define?

A fair number, and worth printing. Retimer and redriver, bifurcation, ASPM, ECRC, the exact phrase replay buffer, equalization presets, de-emphasis, SRIS and SRNS, the ATS protocol extension, and the Integrators List are all standard terms of the trade, and none could be traced to a document read here. ASPM is the clearest case: checked in the secondary article and in three Linux kernel documentation pages, found in none. Endpoint, bridge and enumeration, as formal device-type or process names, sit in the same position.

The contrast makes the boundary real. Advanced Error Reporting is defined in section 6.2 of the PCIe base specification, revision 7.0, as currently cited by the Linux kernel error-recovery documentation, and Downstream Port Containment in section 6.2.11, where a detected error disables the link to the sub-hierarchy below the faulting device until a reset completes. SR-IOV with its Physical and Virtual Functions, the eye diagram read against the unit interval, an open eye meaning low distortion and a closed one meaning risked bit errors, and six Base Address Registers mapping regions from 16 bytes to 2 GB all carry a source.

Keep the two lists apart: one is vocabulary you inherited, the other is vocabulary you can defend.

Close the loop where the reading started: reread the scope statement of revision 7.1 and note which of the five protocols your project touches. The terms worth verifying will be left standing on the page.