Reading a Receiver Eye Diagram

What the plot builds before it says anything

An eye diagram is not a picture of a waveform. It is a stack of them. The instrument samples the same signal over and over, folds each sample against the unit interval, the bit period, and lays the result on one plot: time within the UI on one axis, voltage on the other. Samples build a two-dimensional histogram, normalized against its fullest bin, and a color gradient makes the density readable: how often the signal sat at each voltage, at each point of the bit period.

That is why the plot consumes captures: tens to hundreds of millions of unit intervals commonly go into a single eye pattern. Twelve thousand UIs of a 1.25 Gbit/s signal give the basic shape; eight million show nuance on the edges that the smaller capture cannot.

An open eye corresponds to minimal signal distortion. A closed one says that intersymbol interference and noise have taken the margin a receiver needed.

Why can two benches disagree over one signal?

Because the same waveform yields different eyes depending on how the plot is sliced, and slicing means deciding where each sample sits within the unit interval. That step decides whether the jitter on screen belongs to the signal.

The method any oscilloscope can do: set the display slightly wider than one UI, trigger on both rising and falling edges, and let persistence stack the traces. That shows noise and shape, and destroys the jitter content: the trigger resynchronizes the plot to every UI, leaving only the instrument's own jitter. Estimating the symbol rate and cutting a capture into fixed UI-sized chunks keeps jitter in principle, but drift accumulates, so it is rarely used in practice. On a signal carrying spread-spectrum clocking, as SATA does, a fixed-rate slice grossly exaggerates jitter the receiver is built to track.

The remaining slicing methods are treated on the eye pattern reference page, including the case where a protocol supplies a reference clock, as HDMI does.

The clock a PCIe receiver already builds

Most high-speed serial signals, PCIe among them, use a line code chosen to make clock recovery by PLL easy. Since that is how the real receiver works, the most accurate slicing implements a PLL with the same characteristics in software. Configured well, it conceals spread-spectrum clocking and other long-term variation in the symbol rate, which do not produce errors, while still showing the faster jitter that does.

None of this happens on a link that is not up: that bring-up is what link training covers, and the eye is measured on a link already operating.

What does a real channel do to the shape?

Loss in board traces and cables rises with frequency, driven by dielectric loss, so the channel behaves as a low-pass filter: rise and fall times stretch, and at a high enough rate the signal never reaches full value on a fast 0-1-0 transition, stabilizing only after a run of identical bits. That reads as vertical closure of the eye. The worked example here is a 1.25 Gbit/s NRZ signal after about 12 feet (3.7 m) of RG-188 coax, loss climbing fairly linearly from 0.1 dB at DC to 9 dB at 6 GHz. The rails still show the voltage the signal finally reaches; as high-frequency loss grows, the shape degrades toward a sinusoid.

Two shapes mislead a reader moving fast. Emphasis adds one extra level per signal value, and at first glance that eye can pass for a PAM signal's; but emphasized levels sit closer to the nominal value, and only some transitions between levels are legal. A stub or impedance mismatch writes its reflection onto the edges: a roughly 1-inch (25 mm) open-circuited stub shows as a step in the rising edge with a round-trip delay near 320 ps, about 0.4 UIs, while three more inches of cable stretch that to about 1280 ps, 1.6 UI, past one unit interval, where the eye closes completely.

Line code changes the count of levels too. PCIe 6.0 moved to PAM4 at 64.0 GT/s per lane, so the eye draws four levels where NRZ draws two; the rate side sits on the encoding and usable bandwidth page.

Turning the shape into numbers a test can fail

The eye earns its place in compliance work because its features map to causes. Four pairings carry most of the reading.

The named measurements run further: eye height, rise and fall time, total, random and deterministic jitter, quality factor, eye signal-to-noise ratio, vertical and horizontal opening. Where a number becomes a pass or a fail, test-and-measurement practice overlays an eye mask, a forbidden template the measured eye has to clear. That term is common industry usage rather than a definition the desk could trace to a document it read.

The eye diagram document no one can fetch anymore

One address sits behind the receiver eye diagram's place in PCI Express history: document 300312-001, cited in June 2004 by the Intel E7525 Memory Controller Hub datasheet in its passage on the receiver compliance eye diagram. It could not be retrieved in 2026, from Intel, from PCI-SIG, or from the Internet Archive. This page therefore says the document cannot be found today, and nothing about what it contained. What passing a workshop certifies is a separate question, taken up in how a compliance program works.

What is still testable is on your bench: build the eye from a capture you sized, slice it the way the receiver slices it, and read the four features above against the channel you have.