Link equalization in PCI express

Equalization becomes necessary above 5 GT/s because the channel stops behaving like a simple wire. At 8 GT/s and above, the unit interval is short enough that skin effect, dielectric loss and reflections smear each bit into its neighbours, so a transmitter that only switches between two levels can no longer open the eye at the far end. The link therefore measures the channel and adjusts both ends before it carries traffic, and that adjustment is negotiated during training rather than configured by hand.

The same problem appears in other engineering disciplines, where a design is only as good as the assumptions behind it: a reader who wants to see how a project moves from business case to opening can follow how a road project gets built, and the logic of staged approval and verification is not far from what a PCIe link does at 8 GT/s.

Why does equalization become necessary above 5 GT/s?

At 2.5 GT/s and 5 GT/s, the channel is short enough in electrical terms that a transmitter can drive a non-return-to-zero signal and the receiver can still sample it with a reasonable eye. The loss at the Nyquist frequency of the signal is modest, and the reflections from vias, connectors and package transitions arrive late enough that they do not dominate the sampling instant.

At 8 GT/s the unit interval is 125 ps. Loss rises with frequency, and the Nyquist content of the signal sits high enough that a passive channel attenuates it heavily. Inter-symbol interference spreads each bit into the following ones, and the eye closes. A transmitter that only offers de-emphasis, as at 5 GT/s, cannot compensate for a channel whose loss profile varies from one board to the next.

Equalization is the answer: the transmitter pre-distorts the signal with a finite impulse response filter, and the receiver applies a decision feedback equalizer or a continuous time linear equalizer to undo what the channel did. Because the required settings depend on the actual channel, they cannot be fixed at design time. They are measured and negotiated at link training.

What does the training sequence negotiate?

The training sequence, defined in the PCI Express Base Specification, exchanges ordered sets between the two ports. In the equalization phases, the two ends agree on a set of transmitter coefficients and receiver settings that produce an acceptable eye at the receiver.

The negotiation covers the transmitter FIR coefficients, typically a three-tap preset with pre-cursor, cursor and post-cursor weights, and the receiver's own equalizer settings. The two ports also agree on which lane is being tuned, since equalization proceeds lane by lane, and on the preset or preset range each side will use as a starting point.

The sequence is not a single message. It is a back-and-forth: one port sends a training sequence with a known pattern, the other measures the result and requests a change, and the exchange repeats until the measured eye meets the criteria or the retry limit is reached. The result is a per-lane agreement, not a global one, because each lane sees a slightly different channel.

Where does equalization sit in the link training state machine?

Link training proceeds through states that bring the link from Detect to L0. Equalization sits after the bit lock and symbol lock states, and after the lane-to-lane deskew that establishes a common reference. It is part of the configuration phase, before the link enters L0 and carries TLPs.

The ordering matters. Bit lock and symbol lock must be achieved first, because the receiver cannot measure an eye until it can sample the incoming symbols. Deskew must be done next, because equalization is evaluated per lane and the lanes must be aligned before the results are meaningful. Only then does the state machine enter the equalization phases, and only after those phases complete does the link move to L0.

A link that fails equalization does not silently pass traffic. It either retries within the training sequence or falls back to a lower data rate, depending on what the two ports support and how they are configured.

The equalization stages