Generations
Rate negotiation between PCIe generations
Two PCI Express ports agree on a rate by advertising the speeds each one supports during link training, then settling on the highest rate that appears in both lists.
Two PCI Express ports agree on a rate by advertising the speeds each one supports during link training, then settling on the highest rate that appears in both lists. The exchange happens in the TS1 and TS2 ordered sets before the link leaves Configuration, and the result is fixed for that link until it is retrained. If no common rate above the base exists, the link falls back to 2.5 GT/s, and the board runs below the rate its silicon and layout were designed for.
The negotiation is not a conversation in the usual sense. Each side transmits its own capability set, reads the other side's set, and both compute the same intersection. That symmetry is what makes the result deterministic: two ports that share Gen3 and Gen4 will both land on Gen4, regardless of which one is the downstream port.
For readers who track how satellite operators publish their own ground segment specifications, the same logic of advertised capability and agreed common mode appears in choosing satellite data asia workflows, where a receiving station and a downlink must agree on a modulation and coding pair before a pass is useful. The parallel is structural, not technical: in both cases the slower side sets the ceiling.
How do two ports agree on a rate?
During the Polling and Configuration substates of Link Training and Status State Machine, each transmitter sends TS1 ordered sets. Those sets carry a symbol called the Link and Lane Numbers, but the rate information travels in the training sequences defined for each generation. A port that supports Gen4 will advertise Gen4 capability; a port limited to Gen3 advertises Gen3. When a port receives a set that names a rate it does not support, it does not simply ignore it: it responds with the highest rate it does support, and the two sides converge downward until they find a match.
The convergence is bounded. The base rate of 2.5 GT/s is mandatory for every PCIe port, so there is always a common rate to find. Above that, the shared set can be empty, and the link will stay at 2.5 GT/s. This is why a Gen4 device plugged into a Gen2 slot trains at Gen2, and why a Gen5 device in a Gen4 slot trains at Gen4. The link does not fail; it settles.
Once both sides have exchanged TS2 sets with the agreed rate, the link enters Recovery and then L0. The negotiated rate is recorded in the Link Status register, and software can read it. A retrain, whether triggered by a hot reset, a link disable, or a recovery event, restarts the process from the advertised sets.
What is advertised during training?
Each port advertises two things that matter for rate: the set of rates it supports, and the lane configuration it can use. The rate advertisement is implicit in the training sequences: a port that can transmit at 8.0 GT/s will send TS1 sets that include the Gen3 symbols, and a port that cannot will not. There is no separate "capability register" exchanged over the wire during training; the advertisement is the training sequence itself.
The supported link rates are also visible to software through the Link Capabilities register, which lists the rates the port can use. That register is read by configuration software and by the operating system, but it does not participate in the training negotiation. It is a report, not a vote.
What each side does not advertise is the reason it might be limited. A port may be limited by its PHY, by the reference clock architecture, by the board layout, or by a firmware setting. None of that is visible on the link. The other side sees only the rate set, and negotiates against it.
| Step | What is exchanged | What it settles |
|---|---|---|
| Detect | Receiver detection on each lane | Whether a receiver is present |
| Polling | TS1 ordered sets with supported rate symbols | The candidate rate set |
| Configuration | TS1 and TS2 sets with link and lane numbers | Lane width and lane reversal |
| Rate agreement | TS2 sets naming the highest common rate | The link rate for L0 |
| Recovery | Retraining sequences if the rate changes | Re-entry to L0 at the new rate |
| L0 | Idle ordered sets | Steady-state operation |
What does a fallback cost?
A fallback below the board's design rate costs bandwidth in direct proportion to the rate ratio. A link designed for 16.0 GT/s that trains at 8.0 GT/s carries half the payload per unit time, before encoding overhead. At 128b/130b encoding, the usable throughput at Gen4 x4 is roughly 7.877 GB/s; at Gen3 x4 it is roughly 3.938 GB/s. The halving is not a marginal loss; it changes what workloads are viable on that slot.
The cost is not only throughput. A fallback can also change latency behavior, because a narrower or slower link may require more transactions in flight to keep the same bandwidth, and it can change power behavior, since the link may spend more time in active states to move the same data. For a GPU, a NIC, or an NVMe array, the practical effect is a ceiling that no driver setting can raise.
The fallback is also a signal. If a board that should train at Gen4 comes up at Gen2, the cause is usually physical: a connector, a riser, a trace, or a reference clock that does not meet the signal integrity budget for the higher rate. The negotiation is doing its job by refusing a rate the channel cannot carry reliably.
Checklist when a link comes up slower than expected
- Read the Link Status register and confirm the negotiated rate, not the rate you expected.
- Read the Link Capabilities register on both ends and confirm the advertised rate sets.
- Check the slot's electrical specification: a mechanical x16 slot may be wired for fewer lanes or a lower rate.
- Check for a riser, extender, or adapter between the device and the root complex.
- Check the reference clock architecture: common clock and separate clock configurations have different budgets.
- Check firmware or BIOS settings that cap the link rate or lane width.
- Check the device's own configuration space for a rate limit set by the vendor.
- Retrain the link and confirm the result is stable across several attempts.
Common mistakes
- Treating the Link Capabilities register as the negotiated rate. The capabilities register reports what the port can do; the status register reports what the link actually did. Confusing the two leads to a diagnosis that never matches the symptom.
- Assuming a slower link means a broken device. In most cases the device is working correctly and the channel cannot support the higher rate. Replacing the device before checking the channel wastes time.
- Ignoring the lane width. A link that trains at the expected rate but at half the lanes has the same throughput cost as a rate fallback, and the two are often confused when only one number is read.
- Forcing a rate in firmware without checking the channel. A forced rate that the channel cannot carry will produce link errors, retraining, or a link that never reaches L0. The negotiation exists to prevent that outcome.
- Reading the rate once and assuming it is stable. A link that trains at Gen4 and then drops to Gen3 under load is telling you something about the channel that a single reading at idle will not show.
The page behind these facts
The figures on this page are read from the source the text names, pcisig.com, consulted on September 6, 2026. How this desk reads a document, and what it does with a figure it cannot source, is set out in sources and method.