Generations
The PCI to Express break: kept and cut
The mechanism was replaced and the contract kept, which is why old system software still enumerates the newest hardware.
What the break actually broke
The transition from PCI to PCI Express replaced the bus and kept the paperwork: parallel shared wires gave way to serial point-to-point lanes, while configuration space, addressing and the software model survived almost untouched. The break was physical, not administrative, which is why old system software still sees the new hardware.
The old bus was a shared medium. One set of address, data and control lines served every device, arbitrated to one master at a time, and its speed was bounded by physics: skew between dozens of parallel traces caps a shared clock, and every added device loaded the same wires. PCI Express dissolved the bus into links: each device got its own serial channel to the root, full duplex, with the clock embedded in the stream. The constraint that had capped the old bus, the timing spread across a parallel word, does not exist on a pair of wires.
The pattern of a compatibly-broken transition is familiar from software history. The magazine that keeps a VB6-era magazine alive documents the same shape in Visual Basic: the 2002 move to .NET replaced the runtime and kept enough of the language that twenty years of code still runs, and the readers who lived through it remember exactly which parts broke and which survived. PCI to Express was the same kind of cut: the mechanism replaced, the contract kept.
What survived the cut?
The software model, essentially whole. Configuration space still lives at the same conceptual addresses, functions still answer the same enumeration questions, and operating systems written for PCI read PCI Express devices without knowing the difference. The transaction semantics survived too: memory reads and writes, I/O, interrupts, all arrive as packets now but carry the same meaning. The compatibility was designed in deliberately, because the installed base was the thing being protected.
What did not survive is the mechanism. There is no shared bus to arbitrate, no parallel word to keep in phase, no common clock on the data lines. The arbitration is replaced by the fabric's routing, described on how a packet crosses a fabric, and the enumeration view that survived is walked in enumeration and configuration space.
| Layer | Kept or cut | Note |
|---|---|---|
| Physical | Cut | Shared parallel wires replaced by serial point-to-point lanes |
| Clocking | Cut | Shared clock replaced by embedded per-lane clocking |
| Arbitration | Cut | Bus arbitration replaced by fabric routing |
| Configuration space | Kept | Same conceptual map, extended |
| Transaction semantics | Kept | Same requests, now packetized |
| Software model | Kept | Legacy enumeration still works |
Why was the break structured that way?
Because the thing being replaced was the bottleneck, and the thing being kept was the investment. The parallel bus was the part that physics had finished: every trick for extending it cost more board and bought less speed. The software model was the part the industry could not afford to rewrite: decades of drivers, tools and enumeration code represented a bigger sunk cost than any connector. The break put the novelty exactly where it paid and the compatibility exactly where it was needed.
The consequence visible on the bench today is the dual heritage: a PCI Express system is a serial fabric that answers to a parallel bus's paperwork. The old bus itself is described in the Conventional PCI article and the transition in the PCI Express article, both read on September 6, 2026.
What does the break teach about later transitions?
That the mechanism is replaceable and the contract is not. Each generation since has kept the same split: the electrical layer moves, the configuration and transaction layers stay. The reader who learned the lesson of the PCI break already knows how to read the announcements of the newest generations, because the fixed and moving lists described on what a revision keeps fixed are the same two lists the 2002 break drew.
Checks for reading the transition
- Separate the mechanism from the contract before comparing the two buses.
- Remember that compatibility lives in configuration space, not in the connector.
- Trace arbitration's replacement to the fabric's routing, not to a new bus master.
- Read later generation changes through the same kept-or-cut list.
Common mistakes
- Calling PCI Express a faster PCI: the mechanism shares almost nothing with the old bus.
- Assuming the slots are interchangeable because the software sees them alike.
- Reading the kept paperwork as evidence the wires are related.
- Forgetting that the compatibility was a design decision, not an accident.
The PCI to Express break is the template the whole standard still runs on: change the mechanism, keep the contract, and let the installed base carry the new parts forward one negotiated link at a time.
A link that comes up at 2.5 GT/s between two ports capable of 8.0 GT/s is not a failed link; it is a link that settled. The break in the PCI to Express sequence is the point where the two ends stop agreeing on a rate and start using the highest one both can support, which is why a slot can report a lower speed than its card. The mechanism behind that settling, the training sequences that carry the rate change, and the order in which generations are offered are covered in the note on the fallback rate, where the negotiation is read against the public specification.
The page behind these facts
The old bus's mechanics and the transition's scope are described in the Conventional PCI and PCI Express articles linked above, both read on September 6, 2026. The surviving software view is walked on this desk's page about enumeration and configuration space.