IP Cores, Verification Models and Who Buys Them

A core is a license, not a part you can hold

Ask what a firm sells when it sells PCI Express silicon and the answer splits in two. Some sell finished chips. Others license building blocks: reusable, pre-verified logic or layout, a controller design or a PHY design, handed to a chip maker who folds them into a part of its own. None of that describes a part you can hold. What changes hands is the right to build the block into someone else's silicon.

The rest of the chain follows. A part carrying a licensed block is usually an application-specific integrated circuit, fabricated for one function instead of reprogrammed after manufacture, and it is built at a foundry, a plant that manufactures to a customer's design specification. The other path runs through configurable logic, where endpoints, root ports and switches get implemented or prototyped in flexible or lower-volume designs. The parts that tie segments together, bridges and switches, get a category of their own.

Where does a PHY core stop and the controller begin?

Between the two sits a digital boundary, and that boundary is why a PHY can be designed once and carried into many products. The document that fixes it is the PIPE interface specification, historically published by Intel, which defines a standard interface between a MAC or controller layer and an analog PHY so that one PHY can serve several serial I/O protocols: PCI Express, SATA, USB 3.x and USB4, and DisplayPort.

The desk downloaded and read the current revision on September 6, 2026. Its scope statement ties the revision to implementations conforming to the PCI Express base specification, Revision 7.0, and, in the same sentence, to SATA 3.0, USB 3.2, DisplayPort 2.0 and USB4 v2.0. Feedback on the document goes to an address printed inside it, [email protected].

What the document fixes, and what it leaves open

Its rate tables name seven PCI Express signaling rates, 2.5, 5.0, 8, 16, 32, 64 and 128 GT/s, each with the PCLK frequencies and interface widths a PHY may present for it. Its layer table names the encodings a PHY may implement, and the table of contents ties 128b/130b to PCIe 8, 16 and 32 GT/s. That is the same ladder the desk reads under encoding and usable bandwidth, where a lane rate turns into the bytes a link delivers. The sheet below collects what the document read for this page gives.

Can a link be exercised before silicon exists?

That is the question a verification model answers. A bus functional model is a simulation-only model of a PCI Express device or host, used so that chip and IP designers can exercise a design's logic in simulation before real parts exist. The evidence pack the desk keeps flags that definition as background usage in the field rather than as a claim traced to a document read for it, and the distinction belongs in the sentence.

What a simulation reaches for is firmer at the level of names. The PIPE document read for this page names the state machine that brings a link up, the Link Training and Status State Machine, and the desk describes how a link trains on a page of its own. The behavior of each state, and the ordering of every substate, is what that document does not establish.

"the receiver detection operation in the PCIe LTSSM state Detect.Quiet should be bypassed and the LTSSM should automatically proceed to Polling. If the LTSSM transitions back to Detect from Polling due to timeout, it is recommended that a subsequent transition to Polling should occur either upon an electrical idle exit detection or after a 30 to 100 ms timeout."

Where the labels on this page come from

The category names used so far, ip house, foundry, fpga/pld, bfm, are not the desk's coinage. They come from an archived index of this domain, organized by product category, and the paths that index actually captured are the ones listed in the sideband below. The roster page built on that list names no company at all, which is what a category index is for: a category says what a kind of product does, and leaves who makes it to the product page.

One more item belongs here, because it is the honest half of the story. A document numbered 300312-001, cited in June 2004 by an Intel chipset datasheet at an address on this domain, could not be retrieved in 2026 from Intel, from PCI-SIG or from the Internet Archive. The desk writes that it could not be found, and describes nothing of what the document contained.